1. Field of the Invention
The present invention relates to a bus monitoring device, a bus monitoring method, and a program.
Priority is claimed on Japanese Patent Application No. 2011-150082, filed Jul. 6, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In many system large-scale integrations (LSIs) mounted on image processing devices such as a still-image camera, a moving-image camera, a medical endoscope camera, and an industrial endoscope camera, a plurality of embedded processing blocks share one connected dynamic random access memory (DRAM). In the system LSIs as described above, the plurality of embedded processing blocks are connected to a data bus inside each of the system LSIs. Each processing block accesses the DRAM by means of direct memory access (DMA). At this time, a bus arbiter controls access to the DRAM while properly arbitrating a request for access to the DRAM issued from each processing block.
In this bus arbiter, the following two important functions are required. One function is to secure a bus bandwidth of the entire data bus. The other function is to properly arbitrate each processing block.
The bus bandwidth represents an amount of data on the data bus when each processing block accesses the DRAM. As a method of securing the bus bandwidth of the entire data bus, a bank interleaving method is well-known. In bank interleaving, a data transfer is controlled for each bank of the DRAM. The efficiency of data access of the DRAM is improved by performing a process of setting an address of the next bank to be accessed in parallel during a process of a data transfer of a previously accessed bank. However, there is a period in which access is not accepted when the same bank is continuously accessed in the DRAM. Thus, if the same bank is continuously accessed in bank interleaving, a loss time in which the DRAM does not accept the access occurs and therefore the efficiency of data access is degraded. To secure the high efficiency of data access by performing a data transfer process and an address setting process in parallel, it is necessary to sequentially access different banks by means of bank interleaving.
In addition, as a method of arbitrating each processing block, a method of determining priority when access from each processing block to the DRAM is performed is well-known. Priority of access to the DRAM is determined, for example, according to an average value (average bandwidth) between bus bandwidths of each processing block, a capacity of a buffer provided in each processing block, a level of importance of each processing block, or the like. A bus bandwidth necessary for each processing block is secured by preferentially allocating the bus bandwidth to a processing block in which processing fails when access to the DRAM is inhibited for a constant period of time.
In the related art, technology for improving a bus bandwidth of the entire data bus by means of bank interleaving, that is, improving the efficiency of access to data of the DRAM and securing system performance, while securing a bus bandwidth necessary for each processing block is disclosed.
In Japanese Unexamined Patent Application, First Publication No. 2011-003160 (hereinafter referred to as Patent Document 1), technology for setting priority of each processing block in a register and preferentially accepting access by a high-priority processing block to a different bank is disclosed. In addition, in Japanese Unexamined Patent Application, First Publication No. 2011-003161 (hereinafter referred to as Patent Document 2), technology for setting a method of generating a DRAM address according to each processing block in a register and generating a DRAM address so that banks separated from each other among a plurality of processing blocks are accessed is disclosed.
In the technologies disclosed in Patent Documents 1 and 2, it is possible to perform optimum arbitration for securing the system performance by performing proper register settings, for example, according to a type of DRAM, an operation mode of the system, or the like, because each setting can be adjusted in the register settings.
As described above, in the technologies disclosed in Patent Documents 1 and 2, it is possible to adjust opposite demands such as the improvement of a bus bandwidth of the entire data bus and the securement of a bus bandwidth necessary for each processing block according to the register settings.
However, in the technologies disclosed in Patent Documents 1 and 2, when the register settings are not optimum, for example, an operation of the entire system may fail when a bus bandwidth is allocated by preferentially accepting a request of DRAM access of a low-priority processing block or when bank interleaving does not effectively function, leading to the degradation of the bus bandwidth of the entire data bus.
In this case, it is necessary to specify a processing block, which is a cause of the failure of the operation of the entire system, or optimize the register settings. In addition, even when the operation of the entire system does not reach the failure, effective utilization of bank interleaving and analysis of whether or not DRAM data is efficiently accessed are important to optimize the register settings and improve the system performance.
However, there is no method of improving the efficiency of DRAM data access or acquiring information that is a guideline for optimizing register settings. Thus, in the related art, the efficiency of system development is bad, for example, because the system is actually operated after the register settings considered to be optimum are performed when register settings of processing blocks are performed, and an operation of finding settings in which the system does not fail is performed.
Although it is possible to specify a processing block that is a cause of a system failure to a certain extent from changed register settings when the system fails, it may be impossible to analyze the efficiency of data access when the system does not fail.